High-performance digital subcommittee

As compute power is increasingly migrated to large data centers and the cloud, microprocessors face progressively more stringent design constraints. This year´s processor session introduces 5 new processors providing increased performance and power efficiency. In addition to growing core counts, cache size, and thread count, the historical theme of integration continues as voltage regulators are now being implemented on chip. Other papers in this session demonstrate creative self-monitoring and adaptive techniques to meet power and performance design goals.