Title :
Block processing engine for high-throughput wireless communications
Author :
Iacono, Daniele Lo ; Zory, Julien ; Messina, Ettore ; Piazzese, Nicolo
Author_Institution :
Adv. Syst. Technol. Group, STMicroelectron., France
Abstract :
This paper presents the block processing engine (BPE), a programmable architecture specifically suited for high-throughput wireless communications. Thanks to a high degree of parallelism and a consistent use of pipelined processing, the BPE can satisfy the stringent real-time constraints imposed by emerging technologies. Its efficiency has been proven through the implementation of a dual standard frequency domain equalizer supporting 3GPP HSDPA and IEEE 802.11a.
Keywords :
equalisers; frequency-domain analysis; pipeline processing; radiocommunication; wireless LAN; block processing engine; dual standard frequency domain equalizer; high-throughput wireless communications; pipelined processing; programmable architecture; Application specific integrated circuits; Application specific processors; Digital signal processing; Engines; Equalizers; Frequency domain analysis; Multiaccess communication; Parallel processing; Wireless LAN; Wireless communication; ASIP; FDE; HSDPA; VLIW; WLAN;
Conference_Titel :
Wireless Communication Systems, 2005. 2nd International Symposium on
Print_ISBN :
0-7803-9206-X
DOI :
10.1109/ISWCS.2005.1547668
