Architectural considerations for SF-core based microprocessor

Author

Shacham, A. ; Levy, Y. ; Bronstein, Z. ; Loewenstein, E. ; Bruck, D.M. ; Deitcher, D.

Author_Institution

Nat. Semicond. Ltd., Herzlia, Israel

fYear

1991

fDate

14-16 Oct 1991

Firstpage

21

Lastpage

24

Abstract

The newest member of National Semiconductor´s Series 32000/EP family of Embedded System Processors is a 100 MIPS superscalar RISC microprocessor incorporating over 1,000,000 transistors. It contains a RISC core, called the SF-core, and additional modules integrated on the same chip. The SF-core incorporates two integer units, an optional IEEE-754 compatible floating-point unit (FPU), digital signal processing (DSP) enhancements, and instruction and data caches. Additional integrated modules are a two-channel direct memory access (DMA) controller, a 15-level interrupt control unit (ICU) and a 16-bit timer. The system interface is optimized to support high-performance cost-sensitive designs, achieving a peak performance of 100 MIPS/50 MFLOPS in 25 MHz systems. Due to its DSP capabilities, the SF-core performs 1024 points integer FFT in 1498 μs and 1024 points floating-point FFT in 1025 μs. Other features support multiprocessing and fault-tolerant systems. This microprocessor is fabricated in a 0.8 μm dual-metal CMOS process

Keywords

CMOS integrated circuits; microprocessor chips; reduced instruction set computing; 0.8 μm dual-metal CMOS process; 100 MIPS; 100 MIPS superscalar RISC microprocessor; 1024 points floating-point FFT; 1024 points integer FFT; 16-bit timer; 25 MHz; 50 FLOPS; Embedded System Processors; RISC core; SF-core based microprocessor; Series 32000/EP family; data caches; digital signal processing; fault-tolerant systems; high-performance cost-sensitive designs; instruction cache; integer units; interrupt control unit; multiprocessing; optional IEEE-754 compatible floating-point unit; two-channel DMA controller; two-channel direct memory access; Color; Computational modeling; Computer architecture; Digital signal processing; Digital signal processing chips; Embedded system; Microprocessors; Printers; Process design; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2270-9

Type

conf

DOI

10.1109/ICCD.1991.139834

Filename

139834