A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses

A guarantee obligation of keeping the cell-margin against a simultaneously read and write (R/W) disturbed accesses in the same column is required to a 2-port SRAM. We verified that it is difficult to provide these margins without any decrease in cell-current and any increase in cell-area penalty only by using the previously proposed techniques so far. To solve this, we have developed the new cell design technology for an 8-Tr 2-port cell in a 65-nm CMOS technology and have demonstrated that the R/W margins can be improved by 45%/70%, respectively at 0.9V, and the cell-size can be reduced by 20% compared with the conventional column-based Vdd control. Another 7-Tr cell which can reduce cell-area by 31% has been also demonstrated