Title :
A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment
Author :
Morita, Yasuhiro ; Fujiwara, Hidehiro ; Noguchi, Hiroki ; Kawakami, Kentaro ; Miyakoshi, Junichi ; Mikami, Shinji ; Nii, Koji ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko
Author_Institution :
Graduate Sch. of Natural Sci. & Technol., Kanazawa Univ.
Abstract :
This paper proposes a voltage-control scheme for an SRAM that makes a minimum operation voltage down to 0.3 V even on a future memory-rich SoC. A self-aligned timing control guarantees stable operation in a wide range of Vdd under DVS environment. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that 30% power reduction is achieved at 100 MHz. The area overhead is only 5.6%
Keywords :
SRAM chips; low-power electronics; system-on-chip; 0.3 V; 100 MHz; 64 kByte; 90 nm; SRAM; area overhead; dynamic voltage scaling; self-aligned timing control; system-on-chip; Control systems; Fabrication; Frequency; MOSFETs; Negative bias temperature instability; Power measurement; Random access memory; Threshold voltage; Timing; Voltage control;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705288
