• DocumentCode
    2626726
  • Title

    An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

  • Author

    Pilo, Harold ; Barwin, John ; Braceras, Geordie ; Browning, Christopher ; Burns, Steve ; Gabric, John ; Lamphier, Steve ; Miller, Mark ; Roberts, A. ; Towler, Fred

  • Author_Institution
    IBM Syst. & Technol. Group, Essex Junction, VT
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    15
  • Lastpage
    16
  • Abstract
    This paper describes a 32Mb SRAM that has been designed and fabricated in a 65nm low-power CMOS technology. The design has also been migrated to 45nm bulk and SOI technologies. The 68mm die features read and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms
  • Keywords
    CMOS memory circuits; SRAM chips; nanoelectronics; silicon-on-insulator; 32 kByte; 45 nm; 65 nm; 68 mm; CMOS technology; SRAM design; read and write-assist circuit; silicon-on-insulator; CMOS technology; Circuits; Fluctuations; Manufacturing; Power generation; Random access memory; Rivers; Stability; Voltage; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    1-4244-0006-6
  • Type

    conf

  • DOI
    10.1109/VLSIC.2006.1705289
  • Filename
    1705289
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2626726