Title :
A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits
Author :
Ohbayashi, S. ; Yabuuchi, M. ; Nii, K. ; Tsukamoto, Y. ; Imaoka, S. ; Oda, Y. ; Igarashi, M. ; Takeuchi, M. ; Kawashima, H. ; Makino, H. ; Yamaguchi, Y. ; Tsukamoto, K. ; Inuishi, M. ; Ishibashi, K. ; Shinohara, H.
Author_Institution :
Renesas Technol. Corp., Itami
Abstract :
We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494 mum2 SRAM cell with a beta ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65 nm LSTP CMOS technology
Keywords :
CMOS memory circuits; SRAM chips; embedded systems; system-on-chip; 65 nm; 6T-SRAM design; LSTP CMOS technology; assist circuit; read and write cell stabilizing circuits; system-on-chip; CMOS technology; Circuit stability; Degradation; Electric variables; Intrusion detection; MOS devices; Manufacturing; Random access memory; Rats; Signal to noise ratio;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705290
