Title :
Process defect trends and strategic test gaps
Author :
Ryan, Paul G. ; Aziz, Irfan ; Howell, William B. ; Janczak, Teresa K. ; Lu, Davia J.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
Lithography challenges are beginning to replace `FAB dirt´ as the more challenging source of defects to detect and screen at test. These new defects often cause marginal behaviors, not gross failures, with subtle signatures that differ significantly from both traditional defects and from parametric process variation. Testing for subtle marginalities in effectively random locations exposes important gaps in prevalent test strategies: the strongest marginality screens focus on fixed locations, and the strongest random defect screens look for grosser signatures. These trends and gaps will drive critical new requirements for fault modeling, test generation and test application, and implementing them effectively will require a new level of collaboration between process and product developers.
Keywords :
fault simulation; integrated circuit modelling; lithography; FAB dirt; fault modeling; fixed locations; lithography challenges; marginal behaviors; parametric process variation; prevalent test strategies; process defect trends; process developers; product developers; random defect screens; strategic test gaps; test application; test generation; Circuit faults; Integrated circuit modeling; Lithography; Logic gates; Silicon; Standards;
Conference_Titel :
Test Conference (ITC), 2014 IEEE International
Conference_Location :
Seattle, WA
DOI :
10.1109/TEST.2014.7035276