Analog fault models: Back to the future?

Is it possible to create analog fault models that are theoretically valid, experimentally verifiable, and computationally efficient to support test developments and quality improvements? This presentation challenges the audience to face this question heads-on, given the variety of analog fault models in use in the past twenty years. We will review various efforts, from those relying on mapping manufacturing defects to devices and circuits to others relying on process variations, block-level parametric variations, and circuit-level specification variations. While the impediments to the development of a standard analog fault model are obvious, the procedures to create such a model have never been elucidated, always left as future work to be done later. Well, the future is now. The presentation, with audience participation, seeks to outline possible procedures to solve this problem defined in the past yet still continuing to affect current and future technologies.