Title :
A 64 Mb MROM with good pair selection architecture
Author :
Nakahara, Kazunori ; Hatanaka, Hiroyuki ; Kura, Syuji ; Suminaga, Yasuo ; Hotta, Yasuhiro ; Okada, Mikiro ; Miyata, Keiichi
Author_Institution :
Sharp Integrated Circuits Group, Nara, Japan
Abstract :
The needs for high density mask programmable ROM (MROM) have increased rapidly due to the demand for storing the Kanji character fonts and dictionaries used in Japanese word processors. For example, desktop publishing uses MROMs for 80 M bits fixed data. The authors describe a 64 Mb MROM which employs a `good pair selection´ as a type of redundancy technique. Employing the technology a flat cell structure and a bank selection architecture and a 0.8 μm CMOS process, they have developed high density 64 Mb MROM
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; read-only storage; redundancy; 0.8 micron; 64 Mbit; CMOS; Japanese word processors; Kanji character fonts storage; MROM; WSI; bank selection architecture; desktop publishing; flat cell structure; good pair selection architecture; high density mask programmable ROM; redundancy technique; Assembly; CMOS process; CMOS technology; Ion implantation; Publishing; Read only memory; Switches; Very large scale integration; Wafer bonding; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
DOI :
10.1109/ICWSI.1990.63883
