A 10MS/s 11-b 0.19mm/sup 2/ Algorithmic ADC with Improved Clocking

Author

Kim, Min Gyu ; Hanumolu, Pavan Kumar ; Moon, Un-Ku

Author_Institution

Sch. of the Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR

fYear

0

fDate

0-0 0

Firstpage

49

Lastpage

50

Abstract

A 10Ms/s 11-b algorithmic ADC with an active area of 0.19mm² is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression to reduce area and power, and achieve high linearity. The ADC implemented in a 0.13mum thick gate-oxide CMOS process achieves 69dB SFDR, 58dB SNR, and 56dB SNDR, while consuming 3.5mA from 3V supply

Keywords

CMOS integrated circuits; analogue-digital conversion; clocks; integrated circuit design; logic design; 0.13 micron; 3 V; 3.5 mA; CMOS process; DC offset cancellation; algorithmic ADC; amplifier sharing; analog-digital converter; high linearity; improved clocking; input memory effect suppression; thick gate-oxide; Algorithm design and analysis; Analog-digital conversion; CMOS process; Clocks; Degradation; Digital-analog conversion; High power amplifiers; Linearity; Moon; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705306

Filename

1705306