DocumentCode :
262718
Title :
Achieving extreme scan compression for SoC Designs
Author :
Wohl, Peter ; Waicukauski, John A. ; Colburn, Jonathon E. ; Sonawane, Milind
Author_Institution :
Synopsys Inc., USA
fYear :
2014
fDate :
20-23 Oct. 2014
Firstpage :
1
Lastpage :
8
Abstract :
High volume testing of complex System on Chip (SoC) designs at reasonable test cost requires high test data and test time compression. We present a multilevel scan compression architecture that combines a flexible test compression core with an efficient dynamic broadcast structure and a high speed data access technique. Full X-tolerance, power-aware scan shift and diagnosis are supported through the entire architecture. We present a flow for assembling the various components that limits the impact on area and timing by minimizing test signals and improving modularity of the inserted design-for-test (DFT) structures. These techniques provided a reduction of 600x in test data volume and over 2300x in test time on large Graphics Processor Units (GPU) designs.
Keywords :
assembling; design for testability; graphics processing units; integrated circuit design; integrated circuit testing; system-on-chip; DFT structures; GPU designs; SoC designs; X-tolerance; assembling; complex system on chip designs; design-for-test structures; dynamic broadcast structure; extreme scan compression; flexible test compression core; graphics processor units designs; high speed data access technique; high volume testing; modularity improvement; multilevel scan compression architecture; power-aware scan shift; Clocks; Codecs; Multiplexing; Pins; Pipelines; System-on-chip; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference (ITC), 2014 IEEE International
Conference_Location :
Seattle, WA
Type :
conf
DOI :
10.1109/TEST.2014.7035294
Filename :
7035294
Link To Document :
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