A 0.9-V 96-/spl mu/W Digital Hearing Aid Chip with Heterogeneous S-D DAC

Author

Sunyoung Kim ; Namjun Cho ; Seong-Jun Song ; Donghyun Kim ; Kwanho Kim

Author_Institution

Dept. of Electron. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon

fYear

0

fDate

0-0 0

Firstpage

55

Lastpage

56

Abstract

A full chip implementation of a low-power digital hearing aid is reported. It is composed of preamplifier, Sigma-Delta ADC, DSP and Sigma-Delta DAC with low-power technique. The hardwired DSP has 6 parameters to reduce power consumption with high flexibility. The Sigma-Delta DAC adopts heterogeneous frequency to reduce power consumption further. The proposed digital hearing aid chip achieves 79-dB peak SNR and dissipates 96-muW from a single 0.9-V supply. The core area is 2.7-mm² in a 0.18-mum standard CMOS technology

Keywords

CMOS integrated circuits; analogue-digital conversion; digital signal processing chips; digital-analogue conversion; hearing aids; integrated circuit design; low-power electronics; preamplifiers; sigma-delta modulation; 0.18 micron; 0.9 V; 96 muW; Sigma-Delta ADC; digital hearing aid chip; hardwired DSP; heterogeneous Sigma-Delta DAC; low-power digital hearing aid; low-power technique; preamplifier; standard CMOS technology; Auditory system; Band pass filters; CMOS technology; Digital signal processing; Digital signal processing chips; Energy consumption; Finite impulse response filter; Frequency; Preamplifiers; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705309

Filename

1705309