DocumentCode :
2627222
Title :
A fully pipelined parallel CORDIC architecture for half-pel motion estimation
Author :
Jie Chen ; Liu, K.J.R.
Author_Institution :
Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
Volume :
2
fYear :
1997
fDate :
26-29 Oct. 1997
Firstpage :
574
Abstract :
Based on the concept of pseudo-phase and the sinusoidal orthogonal principles, we design a novel low-complexity and high throughput CORDIC (COordinate Rotation Digital Computer) architecture for half-pel motion estimation. The proposed multiplier-free and fully-pipelined parallel architecture works solely at DCT domain without interpolation of input images to meet the needs of high-quality high-bit rate video communications. In addition, the DCT-based nature enables us to efficiently combine the DCT and motion estimator into one single component of relatively low complexity. Its regular and modular structure along with only local interconnection provides a low-complexity solution for MPEG-2 and H.263 compatible video codec design on a dedicated single chip.
Keywords :
computational complexity; discrete cosine transforms; image processing equipment; motion estimation; parallel architectures; pipeline processing; video codecs; CORDIC architecture; DCT domain; H.263 compatible video codec; MPEG-2; coordinate rotation digital computer; fully-pipelined parallel architecture; half-pel motion estimation; high-quality high-bit rate video communications; local interconnection; low complexity; modular structure; pseudo-phase principle; regular structure; sinusoidal orthogonal principle; Computer architecture; Discrete cosine transforms; Interpolation; Motion estimation; Parallel architectures; Throughput; Video codecs;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Image Processing, 1997. Proceedings., International Conference on
Conference_Location :
Santa Barbara, CA
Print_ISBN :
0-8186-8183-7
Type :
conf
DOI :
10.1109/ICIP.1997.638836
Filename :
638836
Link To Document :
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