A high performance single chip FFT array processor for wafer scale integration

Author

You, Jaehee ; Wong, S. Simon

Author_Institution

Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA

fYear

1990

fDate

23-25 Jan 1990

Firstpage

60

Lastpage

67

Abstract

An architecture with p multiplier-adder´s per butterfly stage has been developed to implement a radix p FFT. It is based on the p-fold symmetry in radix p constant geometry FFT algorithm. A methodology to realize a high radix processing element with lower radix hardware is presented. It is suitable for wafer scale integration. The latency and throughput of this architecture are evaluated. An experimental processor chip to implement a radix 2, 8 point FFT has been successfully designed in CMOS and the results are discussed

Keywords

CMOS integrated circuits; VLSI; cellular arrays; fast Fourier transforms; microprocessor chips; parallel architectures; special purpose computers; CMOS; WSI; experimental processor chip; high radix processing element; latency; lower radix hardware; p multiplier-adder´s per butterfly stage; p-fold symmetry; radix p FFT; radix p constant geometry FFT algorithm; single chip FFT array processor; suitable for wafer scale integration; throughput; wafer scale integration; Computer architecture; Delay; Fast Fourier transforms; Geometry; Hardware; Parallel processing; Signal processing; Signal processing algorithms; Throughput; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-8186-9013-5

Type

conf

DOI

10.1109/ICWSI.1990.63884

Filename

63884