A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers

An on-chip measurement technique for characterizing the jitter tolerance (JTOL) of high-speed receivers is presented. A JTOL test finds the largest sinusoidal jitter (SJ) in the input data stream that the receiver can tolerate and its test typically requires an expensive equipment to impose SJ on the data and long time to repeatedly measure the bit-error rates. The proposed technique emulates the SJ in the off-chip input data stream with a SJ in the on-chip recovered clock of the clock-and-data recovery loop (CDR), allowing an ordinary transmitter to be used as the input source. Furthermore, the testing time is reduced by measuring the CDR bandwidth and timing margin separately, using a linear ramp and step jitters instead of SJ. The in-situ JTOL measurement circuit is demonstrated for a feed-forward phase-interpolating dual-loop CDR, in which the SJ is emulated by applying a digital-valued phase offset to the recovered clock. Implemented in a 65nm CMOS, the circuit occupies only 480μm², 1.8% of the total CDR area. Yet, it can accurately measure the JTOL characteristics of the CDR with 20× shorter testing time.