Title :
A Wide Tracking Range 0.2-4Gbps Clock and Data Recovery Circuit
Author :
Hanumolu, Pavan Kumar ; Wei, Gu-Yeon ; Moon, Un-Ku
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR
Abstract :
A hybrid analog and digital quarter-rate clock and data recovery circuit employs a second-order digital loop filter with delta-sigma truncation to achieve sub-ps phase resolution and better than 2ppm frequency resolution. A test chip fabricated in a 0.18mum CMOS process achieves BER < 10-12 and consumes 14mW power while operating at 2Gbps. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10kHz and 20kHz modulation frequencies respectively, thus, making this CDR suitable for systems with spread spectrum clocking
Keywords :
CMOS integrated circuits; delta-sigma modulation; digital filters; digital phase locked loops; integrated circuit design; integrated circuit testing; 0.18 micron; 0.2 to 4 Gbit/s; 14 mW; CMOS process; clock recovery circuit; data recovery circuit; delta-sigma truncation; second-order digital loop filter; spread spectrum clocking; Bandwidth; Circuits; Clocks; Digital filters; Frequency; Jitter; Oscillators; Phase locked loops; Quantization; Spread spectrum communication;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705317
