• DocumentCode
    2627405
  • Title

    A Sub-Picosecond Resolution 0.5-1.5GHz Digital-to-Phase Converter

  • Author

    Hanumolu, Pavan Kumar ; Kratyuk, Volodymyr ; Wei, Gu-Yeon ; Moon, Un-Ku

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    75
  • Lastpage
    76
  • Abstract
    A digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DLL phase filtering to achieve sub-ps resolution independent of the operating frequency. Test chip fabricated in a 0.13mum CMOS process achieves a DNL below plusmn100fs and plusmn12ps INL and consumes 15mW while operating at 1GHz
  • Keywords
    CMOS integrated circuits; delay lock loops; integrated circuit noise; phase convertors; 0.13 micron; 0.5 to 1.5 GHz; 15 mW; CMOS process; DLL phase filtering; delay locked loop; differential nonlinearity; digital-to-phase converter; integral nonlinearity; noise shaping; Bandwidth; Delay; Filtering; Jitter; Low pass filters; Phase locked loops; Phase noise; Quantization; Transfer functions; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    1-4244-0006-6
  • Type

    conf

  • DOI
    10.1109/VLSIC.2006.1705319
  • Filename
    1705319
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2627405