A Low Power 4.2Gb/s/pin Parallel Link Using Three-Level Differential Encoding

Author

Zogopoulos, Sotirios ; Namgoong, Won

Author_Institution

Dept. of Electr. Eng., Southern California Univ., Los Angeles, CA

fYear

0

fDate

0-0 0

Firstpage

77

Lastpage

78

Abstract

A three-level encoding scheme is proposed to reduce power and increase the data rate in high-speed parallel transceiver system. The proposed encoding scheme transmits 3-bit of information via four pins to overcome the two major problems in single-ended links - reference ambiguity and power line fluctuations - while minimizing power consumption and the effects of inter-symbol interference (ISI). The proposed parallel link, which is designed in 0.18mum CMOS process, achieves a data rate of 4.2Gb/s/pin while dissipating 17.1mW/Gb/s

Keywords

CMOS integrated circuits; encoding; intersymbol interference; low-power electronics; transceivers; 0.18 micron; 3 bit; 4.2 Gbit/s; CMOS process; high-speed parallel transceiver system; inter-symbol interference; low power parallel link; power line fluctuations; reference ambiguity; single-ended links; three-level differential encoding; CMOS process; Decoding; Driver circuits; Encoding; Energy consumption; Fluctuations; Intersymbol interference; Pins; Transceivers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705320

Filename

1705320