DocumentCode :
2627496
Title :
Implementation of configurable hardware using wafer scale integration
Author :
Kean, Tom ; Gray, John ; Pruniaux, Bernard
fYear :
1990
fDate :
23-25 Jan 1990
Firstpage :
68
Lastpage :
73
Abstract :
In recent years a new class of integrated circuits has emerged which can be configured dynamically to implement gate level logic designs. This class of device is termed configurable hardware. These structures can be used to implement important algorithms with much higher performance than conventional computers and board designs using configurable hardware as a computation engine have been proposed. In many ways wafer scale integration of large configurable hardware systems is very attractive for computational applications and this paper considers a wafer scale version of one particular configurable architecture: Configurable Array Logic (CAL) using CMOS
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; microprocessor chips; parallel architectures; CAL; CMOS; Configurable Array Logic; computation engine; configurable hardware; configured dynamically; gate level logic designs; wafer scale integration; Algorithm design and analysis; Application software; Computer applications; Computer architecture; Engines; Hardware; High performance computing; Logic arrays; Logic design; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
Type :
conf
DOI :
10.1109/ICWSI.1990.63885
Filename :
63885
Link To Document :
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