DocumentCode :
2627603
Title :
A parallel lattice basis reduction for mesh-connected processor arrays and parallel complexity
Author :
Heckler, C. ; Thiele, L.
Author_Institution :
Lehrstuchl fuer Mikroelektronik, Saarlandes Univ., Saarbrucken, Germany
fYear :
1993
fDate :
1-4 Dec 1993
Firstpage :
400
Lastpage :
407
Abstract :
Lattice basis reduction has important applications in the areas of computer algebra, cryptography and combinatorial optimization. Several efficient sequential algorithms are known. Recently, parallel algorithms have been developed but until now a formal proof for the efficiency of parallel algorithms with n2 processors has been omitted, where n denotes the dimension of the lattice. In this paper, a variant of the well-known basis reduction algorithms is presented that is well suited for the computation with fast floating point arithmetic and for the implementation on a mesh-connected array of n2 processors. In addition, an error analysis and a proof of the parallel efficiency is provided
Keywords :
computational complexity; floating point arithmetic; parallel algorithms; process algebra; symbol manipulation; basis reduction algorithms; combinatorial optimization; computer algebra; cryptography; fast floating point arithmetic; mesh-connected array; mesh-connected processor arrays; parallel algorithms; parallel complexity; parallel lattice basis reduction; Algebra; Application software; Computational geometry; Concurrent computing; Cryptography; Error analysis; Floating-point arithmetic; Lattices; Parallel algorithms; Polynomials;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing, 1993. Proceedings of the Fifth IEEE Symposium on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-4222-X
Type :
conf
DOI :
10.1109/SPDP.1993.395505
Filename :
395505
Link To Document :
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