Title :
175 GMACS/mW Charge-Mode Adiabatic Mixed-Signal Array Processor
Author :
Karakiewicz, Rafal ; Genov, Roman ; Abbas, Adeel ; Cauwenberghs, Gert
Author_Institution :
Toronto Univ., Ont.
Abstract :
An adiabatic charge-recycling mixed-signal array with integrated resonant clock generator delivers 175 GMACS (multiply-and-accumulates per second) throughput for every mW of power, a ten-fold improvement over the dynamic power incurred when resonant line drivers are replaced with CMOS drivers. The 3-T CID/DRAM cell provides non-destructive 1b-1b multiply accumulation, and integrated quantizers yield 8-bit outputs with +/- 1 LSB worst-case mismatch. The 256 times 512 four-quadrant array is embedded in a processor for template-based face detection
Keywords :
CMOS integrated circuits; DRAM chips; driver circuits; logic design; microprocessor chips; mixed analogue-digital integrated circuits; 3-T CID/DRAM cell; 8 bit; CMOS drivers; adiabatic charge-recycling mixed-signal array; charge-mode adiabatic mixed-signal array processor; four-quadrant array; nondestructive multiply accumulation; resonant clock generator; resonant line drivers; template-based face detection; Charge transfer; Clocks; Computer architecture; Driver circuits; Power dissipation; Power generation; Random access memory; Resonance; Threshold voltage; Throughput;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705329
