DocumentCode
2627674
Title
A Duty-Cycle Correction Circuit for High-Frequency Clocks
Author
Agarwal, Kanak ; Montoye, Robert
Author_Institution
IBM, Austin, TX
fYear
0
fDate
0-0 0
Firstpage
106
Lastpage
107
Abstract
We present a circuit to control duty-cycle of high-frequency clocks with very fine resolution. The proposed duty-cycle detection and correction circuits are digital and do not require external references and matching devices. The circuits are designed to compensate for duty-cycle uncertainties in a floating point unit implemented using limited switch dynamic logic (LSDL) (Belloumini, 2005). The results show that the circuit can correct the duty-cycle of an 8-GHz clock with plusmn0.8% accuracy for an input range of 25% to 75%
Keywords
clocks; floating point arithmetic; logic circuits; 8 GHz; duty-cycle correction circuit; duty-cycle detection circuits; duty-cycle uncertainties; floating point unit; high-frequency clocks; limited switch dynamic logic; Clocks; Counting circuits; Detectors; Frequency measurement; Logic circuits; Logic devices; Ring oscillators; Switches; Time measurement; Uncertainty;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
1-4244-0006-6
Type
conf
DOI
10.1109/VLSIC.2006.1705332
Filename
1705332
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