DocumentCode
2627697
Title
MRAM Cell Technology for Over 500MHz SoC
Author
Sakimura, N. ; Sugibayashi, T. ; Honda, T. ; Honjo, H. ; Saito, S. ; Suzuki, T. ; Ishiwata, N. ; Tahara, S.
Author_Institution
Syst. Devices Res. Labs., NEC Corp., Kanagawa
fYear
0
fDate
0-0 0
Firstpage
108
Lastpage
109
Abstract
We propose two new MRAM cell structures, 2T1MTJ and 5T2MTJ. Although they enable very high-speed operation, they require small-write-current magnetic tunnel junctions (MTJs). We found that write current could be reduced to 1mA by a novel MTJ into which a write line is inserted. The 5T2MTJ cell has two write current switches and a sense circuit. Simulation results show that access time of under 1ns is achieved when the magnetic resistance is 5k-ohm and its ratio (MR) is 150%
Keywords
magnetic tunnelling; random-access storage; system-on-chip; 1 mA; 2T1MTJ cell; 5 kohm; 5T2MTJ cell; MRAM cell structures; MRAM cell technology; magnetic resistance; magnetic tunnel junctions; sense circuit; system-on-chip; write current switches; Circuit testing; Clocks; Frequency; Laboratories; Magnetic field measurement; Magnetic tunneling; Nonvolatile memory; Random access memory; Read-write memory; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
1-4244-0006-6
Type
conf
DOI
10.1109/VLSIC.2006.1705333
Filename
1705333
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