Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation

Author

Ahmadi, Ali ; Ke Huang ; Natarajan, Suriyaprakash ; Carulli, John M. ; Makris, Yiorgos

Author_Institution

Dept. of Electr. Eng., Univ. of Texas at Dallas, Richardson, TX, USA

fYear

2014

fDate

20-23 Oct. 2014

Firstpage

1

Lastpage

10

Abstract

Wafer-level spatial correlation modeling of probetest measurements has been explored in the past as an avenue to test cost and test time reduction. In this work, we first improve the accuracy of a popular Gaussian process-based wafer-level spatial correlation method through two key enhancements: (i) confidence estimation-based progressive sampling, and, (ii) inclusion of spatio-temporal features for inter-wafer trend learning. We then explore a new application of the enhanced correlation modeling method in estimating High Volume Manufacturing (HVM) yield from a small set of early wafers and we demonstrate its effectiveness on a large set of actual industrial test data.

Keywords

Gaussian processes; integrated circuit modelling; integrated circuit testing; integrated circuit yield; Gaussian process-based wafer-level spatial correlation; HVM yield estimation; confidence estimation-based progressive sampling; high volume manufacturing yield; inter-wafer trend learning; probe-test measurements; spatio-temporal features; spatio-temporal wafer-level correlation modeling; Accuracy; Correlation; Gaussian processes; Kernel; Predictive models; Semiconductor device modeling; Training;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference (ITC), 2014 IEEE International

Conference_Location

Seattle, WA

Type

conf

DOI

10.1109/TEST.2014.7035325

Filename

7035325