DocumentCode
2627817
Title
Hardware Aware eIRA LDPC Code Generation
Author
Pérez, Jesùs M. ; Fernandez, Victor
Author_Institution
Microelectronics Eng. Group, Cantabria Univ., Santander
fYear
2005
fDate
7-7 Sept. 2005
Firstpage
438
Lastpage
441
Abstract
This paper presents a new methodology for generating eIRA LDPC codes with low hardware cost. Approach is based on hierarchical matrices and primitive generators. Apart from implementation considerations, proposed method shows good BER performance due to a pseudo-random construction and the absence of length-four cycles. Moreover, low-weight codewords and near-codewords are also considered in order to reduce error floors
Keywords
error statistics; matrix algebra; parity check codes; pseudonoise codes; random codes; BER performance; LDPC code generation; error floor reduction; hierarchical matrices; length-four cycles; primitive generators; pseudorandom construction; Bit error rate; Channel coding; Costs; Floors; Hardware; Hydrogen; Microelectronics; Parity check codes; Sparse matrices; Turbo codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Communication Systems, 2005. 2nd International Symposium on
Conference_Location
Siena
Print_ISBN
0-7803-9206-X
Type
conf
DOI
10.1109/ISWCS.2005.1547738
Filename
1547738
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