Array Processors for Viterbi Decoder

Wireless receivers are often characterized as portable and battery operated. As such, they are bound by a tight set of constraints such as power consumption, area usage, and throughput speed. Parallel implementation of operations increases the speed of computation without an undue increase in lock frequency. Thus, high throughput is achieved without excessive power consumption. The apparent tradeoff in throughput improvement, of parallel implementation, is the larger area usage. Hence, there is a need to find an optimal implementation in terms of area, speed and complexity. In this paper, an exhaustive set of parallel implementations of Viterbi decoder is developed, by different arrangements of processing elements (PEs) and schedules. Objective comparison among various implementations is performed to select the optimal implementation