Title :
A 100-Gb/s 1:2 Demultiplexer
Author :
Suzuki, Yasuyuki ; Mamada, Masayuki ; Yamazaki, Zin
Author_Institution :
Syst. Devices Res. Labs., NEC Corp., Kanagawa
Abstract :
A 100-Gbit/s 1:2 demultiplexer (DEMUX) has been developed using InP HBT technology. The IC features broadband impedance matching with double terminations and transmission lines with a low phase constant in the data and clock distributions to obtain high signal quality and a large timing margin. Excellent eye diagrams with 550-mVp-p output voltage swings and 600-fs rms jitter were obtained. To the best of our knowledge, this is the highest data rate operation yet reported. Moreover, error-free operation for 231 - 1 at 100-Gb/s has been achieved
Keywords :
III-V semiconductors; clocks; demultiplexing equipment; heterojunction bipolar transistors; impedance matching; indium compounds; jitter; optical communication; transmission lines; 100 Gbit/s; 550 mV; 600 fs; DEMUX; HBT; InP; broadband impedance matching; clock distributions; data distributions; demultiplexer; double terminations; error-free operation; eye diagrams; flip-flops; heterojunction bipolar transistors; high-speed integrated circuits; optical communication; signal quality; timing margin; transmission lines; Clocks; Demultiplexing; Flip-flops; Heterojunction bipolar transistors; High speed integrated circuits; Impedance matching; Indium phosphide; Integrated circuit interconnections; Timing; Voltage;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705341
