Title :
Vesuvius-3D: A 3D-DfT demonstrator
Author :
Marinissen, Erik Jan ; De Wachter, Bart ; O´Loughlin, Stephen ; Deutsch, Sergej ; Papameletis, Christos ; Burgherr, Tobias
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
IMEC and Cadence have jointly developed a 3D-DfT architecture that serves both 2.5D- and 3D-SICs. Originally targeting stacks of monolithic logic-only dies, over time this architecture has been extended to include (1) memory-on-logic stacks, (2) complex SOCs, and (3) multi-tower stacks. We have defined and implemented a full automation flow based on Cadence´ RTL Compiler and Encounter Test. To demonstrate the capabilities of the 3D-DfT architecture and associated EDA flow, we designed a 3D-DfT Demonstrator circuit as part of an IMEC 3D chip stack nicknamed `Vesuvius-3D´. This test vehicle consists of two identical dies of 8.1×8.1mm2 in 65nm CMOS processed by GLOBALFOUNDRIES and IMEC. In this paper, we report on the design, test generation, processing, and pre-bond and post-bond measurement results of this 3D-DfT Demonstrator.
Keywords :
CMOS logic circuits; CMOS memory circuits; design for testability; integrated circuit bonding; integrated circuit design; integrated circuit measurement; integrated circuit testing; logic testing; three-dimensional integrated circuits; 2.5D-SIC; 3D-DfT architecture; 3D-DfT demonstrator circuit; 3D-SIC; CMOS; Cadence; EDA flow; GLOBALFOUNDRIES; IMEC 3D chip stack; RTL compiler; SOC; Vesuvius-3D; design for testability; encounter test; memory-on-logic stacks; monolithic logic-only dies; multitower stacks; postbond measurement; prebond measurement; size 65 nm; size 8.1 mm; stacked integrated circuit; test generation; Computer architecture; Integrated circuit interconnections; Layout; Microprocessors; Probes; Stacking; Vehicles;
Conference_Titel :
Test Conference (ITC), 2014 IEEE International
Conference_Location :
Seattle, WA
DOI :
10.1109/TEST.2014.7035332
