A SRAM Core Architecture with Adaptive Cell Bias Scheme

Author

Yu, Hak-soo ; Kim, Nam-Seog ; Son, Young-Jae ; Kim, Yong-Goel ; Kim, Hyo-Chang ; Cho, Uk-Rae ; Byun, Hyun-Geun

Author_Institution

Memory Div., Samsung Electron., Kyeoggi-Do

fYear

0

fDate

0-0 0

Firstpage

128

Lastpage

129

Abstract

This paper describes an adaptive cell bias scheme that is proposed to achieve high performance and stability for a low power, high speed, and high density SRAM core with less process variation. The proposed scheme is featured with constrained-successive cell bias optimization method that determines the optimal cell bias condition sequentially to meet both the speed and stability target of a given SRAM core. The architecture with adaptive cell bias scheme is applied to a 144Mb double stacked S₃ SRAM and leads to 49% reduction in SRAM core performance parameter variations with 8% area overhead. The power reduction is 21%

Keywords

SRAM chips; circuit optimisation; circuit stability; high-speed integrated circuits; integrated circuit design; low-power electronics; memory architecture; 144 MBytes; SRAM core architecture; adaptive cell bias scheme; cell bias optimization; optimal cell bias; power reduction; Adaptive control; Constraint optimization; Controllability; Degradation; Memory architecture; Optimization methods; Programmable control; Random access memory; Stability; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705343

Filename

1705343