Title :
Incremental synthesis for engineering changes
Author :
Watanabe, Yosinori ; Brayton, Robert K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The problem of rectifying design incorrectness due to specification changes as well as design errors of VLSI circuits is formulated and a basic approach using logic synthesis techniques is presented. An efficient approach is presented for rectifying the functional incorrectness by attaching circuitry exterior to the original design. A necessary and sufficient condition for full rectification of the design is provided. It is shown that the proposed approach always succeeds in the rectification of arbitrary combinational circuits. The situation where rectification arises in a practical design process is briefly reviewed
Keywords :
VLSI; combinatorial circuits; logic design; VLSI circuits; combinational circuits; design errors; design incorrectness; engineering changes; full rectification; functional incorrectness; incremental synthesis; logic synthesis; multiple output Boolean networks; specification changes; Automatic logic units; Circuit synthesis; Computer errors; Design automation; Design engineering; Joining processes; Logic design; Process design; Sufficient conditions; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139840