Title :
A 65 nm Ultra-High-Density Dual-Port SRAM with 0.71um/sup ~/ 8T-Cell for SoC
Author :
Nii, K. ; Masuda, Y. ; Yabuuchi, M. ; Tsukamoto, Y. ; Ohbayashi, S. ; Imaoka, S. ; Igarashi, M. ; Tomita, K. ; Tsuboi, N. ; Makino, H. ; Ishibashi, K. ; Shinohara, H.
Author_Institution :
Renesas Technol. Corp., Hyogo
Abstract :
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71mum2 8T-DP-cell, which cell size is 1.44times larger than 6T-single-port (SP) cell
Keywords :
CMOS memory circuits; SRAM chips; circuit stability; memory architecture; nanotechnology; system-on-chip; 32 kBytes; 65 nm; CMOS technology; SoC; access conflict problem; access scheme; cell stability; decoder circuit; dual-port SRAM; CMOS technology; Chip scale packaging; Circuit stability; Circuit testing; Decoding; Image processing; Random access memory; Switches; Timing; Writing;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705344
