• DocumentCode
    2627975
  • Title

    A 6-Bit 800-MS/s Pipelined A/D Converter with Open-Loop Amplifiers

  • Author

    Shen, Ding-Lan ; Lee, Tai-Cheng

  • Author_Institution
    Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    134
  • Lastpage
    135
  • Abstract
    A 6-bit 800-MS/s pipelined A/D converter (ADC) with voltage-mode open-loop amplifiers achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Fabricated in a 0.18mum CMOS technology, the ADC consumes 105 mW from a 1.8-V power supply while the active area is only 0.5-mm2
  • Keywords
    CMOS digital integrated circuits; amplifiers; analogue-digital conversion; open loop systems; 0.18 micron; 1.8 V; 105 mW; 6 bit; CMOS technology; SFDR; SNDR; open-loop amplifiers; pipelined A/D converter; voltage-mode amplifiers; Broadband amplifiers; CMOS technology; Clocks; DVD; Delay; Disk drives; Error correction; Open loop systems; Power supplies; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    1-4244-0006-6
  • Type

    conf

  • DOI
    10.1109/VLSIC.2006.1705346
  • Filename
    1705346
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2627975