A 1-V 100MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

Author

Wu, Ying ; Cheung, Vincent S L ; Luong, Howard

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol.

fYear

0

fDate

0-0 0

Firstpage

136

Lastpage

137

Abstract

A 1V, 8-bit dual-mode ADC is realized using multi-phase switched-opamp (SO) technique. Employing a proposed loading-free pipelined ADC architecture and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100MS/s conversion rate, which is the fastest operation speed reported at 1-V supply, and comparable to many high-voltage switched-capacitor (SC) ADC. Implemented in a 0.18mum CMOS process, the ADC obtains a peak SNR of 45dB and SFDR of 52.6dB while dissipating only 30mW

Keywords

CMOS digital integrated circuits; analogue-digital conversion; high-speed integrated circuits; integrated circuit design; low-power electronics; operational amplifiers; pipeline processing; 0.18 micron; 1 V; 30 mW; 8 bit; CMOS ADC; dual-mode ADC; loading-free architecture; multiphase switched-opamp; pipelined ADC architecture; CMOS process; CMOS technology; Capacitors; Energy consumption; Error correction; Sampling methods; Signal processing; Signal resolution; Switching converters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705347

Filename

1705347