DocumentCode
2628022
Title
A 500MS/s 5b ADC in 65nm CMOS
Author
Ginsburg, Brian P. ; Chandrakasan, Anantha P.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA
fYear
0
fDate
0-0 0
Firstpage
140
Lastpage
141
Abstract
A 1.2V 6mW 500MS/s 5-bit ADC for use in a UWB receiver has been fabricated in a pure digital 65nm CMOS technology. The ADC uses a 6-channel time-interleaved successive approximation register architecture. Each of the channels has a split capacitor array to reduce switching energy and sensitivity to digital timing skew. A variable delay line is used to optimize the instant of latch strobing to reduce preamplifier currents
Keywords
CMOS digital integrated circuits; analogue-digital conversion; capacitors; delay lines; integrated circuit design; nanotechnology; ultra wideband communication; 1.2 V; 5 bit; 6 mW; 65 nm; ADC; UWB receiver; digital CMOS technology; digital timing skew reduction; latch strobing; reduced preamplifier current; split capacitor array; successive approximation register; switching energy reduction; time-interleaved register; CMOS technology; Capacitors; Clocks; Communication switching; Delay lines; Preamplifiers; Robustness; Sampling methods; Switches; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
1-4244-0006-6
Type
conf
DOI
10.1109/VLSIC.2006.1705349
Filename
1705349
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