1.047GHz, 1.2V, 90nm CMOS, 2-Way VLIW DSP Core Using Saturation Anticipator Circuit

Author

Suzuki, H. ; Takata, H. ; Shinohara, H. ; Teraoka, E. ; Matsuo, M. ; Yoshida, T. ; Sato, H. ; Honda, N. ; Masui, N. ; Shimizu, T.

Author_Institution

Renesas Technol. Corp., Hyogo

fYear

0

fDate

0-0 0

Firstpage

152

Lastpage

153

Abstract

1.047GHz synthesizable 2-way VLIW general purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder´s inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP´s clock frequency by 20.8%. The test chip also runs 0. 10muW/MHz at 0.8V low power operation mode

Keywords

CMOS digital integrated circuits; adders; digital signal processing chips; integrated circuit design; low-power electronics; nanotechnology; optimisation; parallel architectures; 0.8 V; 1.047 GHz; 1.2 V; 90 nm; ALU; VLIW DSP core; adder operation; digital CMOS technology; general purpose DSP; logic structure optimization; low power operation; parallel saturation check; saturation anticipator circuit; saturation detection; Adders; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Digital signal processing; Digital signal processing chips; Frequency; Logic circuits; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705355

Filename

1705355