Architectural support for block transfers in a shared-memory multiprocessor

Author

Wilton, Steven J E ; Vranesic, Zvonko G.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

fYear

1993

fDate

1-4 Dec 1993

Firstpage

51

Lastpage

54

Abstract

This paper examines how the performance of a shared-memory multiprocessor can be improved by including hardware support for block transfers. A system similar to the Hector multiprocessor developed at the University of Toronto is used as a base architecture. It is shown that such hardware support can improve the performance of initialization code by as much as 50%, but that the amount of improvement depends on the memory access behavior of the program and the way in which the operating system issues block transfer requests

Keywords

memory architecture; operating systems (computers); performance evaluation; shared memory systems; Hector multiprocessor; architectural support; base architecture; block transfers; hardware support; initialization code; memory access behavior; operating system; performance improvement; shared-memory multiprocessor; Access protocols; Buffer storage; Clocks; Computer architecture; Hardware; Multiprocessor interconnection networks; Operating systems; Process control; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing, 1993. Proceedings of the Fifth IEEE Symposium on

Conference_Location

Dallas, TX

Print_ISBN

0-8186-4222-X

Type

conf

DOI

10.1109/SPDP.1993.395551

Filename

395551