• DocumentCode
    2628349
  • Title

    Cache design for an Explicit Token Store data flow architecture

  • Author

    Shanmugam, Ponnarasu ; Andhare, Shirish ; Kavi, Krishna ; Shirazi, Behrooz ; Hurson, Ali

  • Author_Institution
    Texas Univ., Arlington, TX, USA
  • fYear
    1993
  • fDate
    1-4 Dec 1993
  • Firstpage
    45
  • Lastpage
    50
  • Abstract
    This paper discusses the performance enhancement of an Explicit Token Store (ETS) architecture as a result of the introduction of hierarchical memory system. It indicates how locality can be exploited in a data-flow environment and evaluates a novel cache subsystem design for this purpose. The introduction of an operand cache and an instruction cache, cause a performance enhancement, remarkable enough, to justify their cost. The paper explores various optimizations and resource management schemes to enhance performance further and discusses the costs and trade-offs involved. Some of the ideas discussed in this paper for the ETS architecture are applicable to many fine-grained multithreaded architectures
  • Keywords
    cache storage; data flow computing; memory protocols; performance evaluation; resource allocation; ETS architecture; Explicit Token Store data flow architecture; cache subsystem design; fine-grained multithreaded architectures; hierarchical memory system; instruction cache; locality; operand cache; optimizations; performance enhancement; resource management schemes; trade-offs; Cache memory; Cost function; Flow graphs; Prefetching; Resource management; Spine;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing, 1993. Proceedings of the Fifth IEEE Symposium on
  • Conference_Location
    Dallas, TX
  • Print_ISBN
    0-8186-4222-X
  • Type

    conf

  • DOI
    10.1109/SPDP.1993.395552
  • Filename
    395552