Title :
Execution behavior analysis and performance improvement in shared-memory architectures
Author :
Zhang, Xiaodong ; He, Keqiang ; Butchee, George
Author_Institution :
High-Performance Comput. & Software Lab., Texas Univ., San Antonio, TX, USA
Abstract :
Communications latency forms a major obstacle to effective parallel processing. The bottlenecks of interprocessor communication can be caused by characteristics of a particular architecture or a particular application, and especially by the relationship between the two. We believe that efficient parallel processing requires serious attention to this intersection of architecture and application. In this paper we report: our analysis of the execution behavior of three programs from the SPLASH set, using two multiprocessor systems and a simulator; our identification of one program as especially hostile to multiprocessors; and the results of our efforts to improve the performance of that program by applying our detailed knowledge of the relationship between application and architecture
Keywords :
multiprocessing systems; parallel architectures; parallel processing; performance evaluation; shared memory systems; SPLASH set; bottlenecks; communications latency; execution behavior; interprocessor communication; multiprocessor systems; parallel processing; performance improvement; shared-memory architectures; simulator; Computer architecture; Delay; Fluid dynamics; Helium; Joining processes; Laboratories; Memory management; Message passing; Performance analysis; Performance evaluation;
Conference_Titel :
Parallel and Distributed Processing, 1993. Proceedings of the Fifth IEEE Symposium on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-4222-X
DOI :
10.1109/SPDP.1993.395555
