DfST: Design for secure testability

While manufacturing test necessitates deep access into the Integrated Circuit (IC) to enhance its testability, this can inadvertently threaten the security of the IC in security-critical applications. Although black-box testing ensures security, it fails to deliver high-quality test. Therefore, our goal is to come up with DFT techniques that deliver testability without compromising the security of the IC. We propose various DFT techniques that tackle the testing challenges, such as test time, test data volume, and test power. Furthermore, we propose different scan attacks, which circumvent the security of the IC in the presence of advanced DFT techniques. We identify the limitations of our proposed scan attacks to develop countermeasures that can thwart these attacks.