A Low-Power Receiver with Switched-Capacitor Summation DFE

Author

Emami-Neyestanak, Azita ; Varzaghani, Aida ; Bulzacchelli, John ; Rylyakov, Alexander ; Yang, Chih-Kong Ken ; Friedman, Daniel

Author_Institution

IBM T.J. Watson Res. Center, Yorktown Heights, NY

fYear

0

fDate

0-0 0

Firstpage

192

Lastpage

193

Abstract

A low power receiver with a one tap DFE was fabricated in 90nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition directly at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. At 10Gb/s data rate, the receiver consumes less than 6.0mW from a 1.0V supply

Keywords

CMOS integrated circuits; buffer circuits; decision feedback equalisers; low-power electronics; multiplexing equipment; radio receivers; sample and hold circuits; switched capacitor networks; 1.0 V; 10 Gbit/s; 90 nm; CMOS technology; analog multiplexer; clock buffers; front-end sample-hold circuit; low-power receiver; one tap DFE; power consumption; quarter rate clocking scheme; speculative equalization; switched capacitor; Adders; CMOS technology; Clocks; Decision feedback equalizers; Energy consumption; Integrated circuit interconnections; Intersymbol interference; Multiplexing; Power system interconnection; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705375

Filename

1705375