Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

Author

Cassano, Luca

Author_Institution

Dept. of Inf. Eng., Univ. of Pisa, Pisa, Italy

fYear

2014

fDate

20-23 Oct. 2014

Firstpage

1

Lastpage

10

Abstract

In the Ph.D. thesis1 from which this summary has been extracted the author proposed a framework of methodologies for the analysis and test of the effects of Single Event Upsets (SEUs) in the configuration memory of SRAM-based FPGA systems. In particular, an accurate SEU simulator for the early assessment of the sensitivity of SRAM-based FPGA systems to SEUs has been proposed, as well as a model-checking based untestability analysis methodology and a genetic algorithm-based automatic test pattern generation environment. All the proposed methodologies have been applied to a set of circuits from the ITC´99 benchmark and the SEU simulator has also been applied to the MiniMips microprocessor.

Keywords

SRAM chips; automatic test pattern generation; field programmable gate arrays; formal verification; genetic algorithms; radiation hardening (electronics); sensitivity analysis; ITC´99 benchmark; MiniMips microprocessor; SEU simulator; SRAM-based FPGA systems; configuration memory; genetic algorithm-based automatic test pattern generation environment; model-checking; sensitivity assessment; single event upsets; untestability analysis methodology; Field programmable gate arrays; Logic gates; Routing; Switches; Yttrium; Automatic Test Pattern Generation; Failure Probability; Fault Simulation; SEU Sensitivity; SRAM-based FPGAs; Single Event Upsets; Untestability Analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference (ITC), 2014 IEEE International

Conference_Location

Seattle, WA

Type

conf

DOI

10.1109/TEST.2014.7035366

Filename

7035366