Title : 
Modeling of chip-package resonance in power distribution networks by an impulse response
         
        
            Author : 
Uematsu, Y. ; Osaka, H. ; Yagyu, M. ; Saito, T.
         
        
            Author_Institution : 
Production Eng. Res. Lab. (PERL), Hitachi, Ltd., Yokohama, Japan
         
        
        
        
        
        
            Abstract : 
This paper proposes a method for modeling chip-package resonance using impulse response. To extract chip and package electrical circuit parameters, we assume a circuit equivalent to the loop from the chip to the package decoupling capacitor as the RL-RC parallel circuit and convert it into an RLC parallel circuit. We apply this method to devise an electrical circuit model capable of expressing chip-package resonance with high accuracy, as confirmed by experimental results.
         
        
            Keywords : 
RLC circuits; chip scale packaging; circuit resonance; power supply circuits; RL-RC parallel circuit; RLC parallel circuit; chip package resonance modeling; electrical circuit parameters; impulse response; package decoupling capacitor; power distribution networks; Capacitance; Capacitors; Inductance; Integrated circuit packaging; Power supplies; Power system modeling; Power systems; RLC circuits; Resonance; Semiconductor device measurement;
         
        
        
        
            Conference_Titel : 
Signal Propagation on Interconnects (SPI), 2010 IEEE 14th Workshop on
         
        
            Conference_Location : 
Hildesheim
         
        
            Print_ISBN : 
978-1-4244-7611-4
         
        
        
            DOI : 
10.1109/SPI.2010.5483595