Title :
A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip
Author :
Jumel, F. ; Royannez, Philippe ; Mair, H. ; Scott, D. ; Er Rachidi, A. ; Lagerquist, Rolf ; Chau, Marie ; Gururajarao, S. ; Thiruvengadam, S. ; Clinton, Michael ; Menezes, V. ; Hollingsworth, R. ; Vaccani, J. ; Piacibello, F. ; Culp, N. ; Rosal, J. ; Ball
Author_Institution :
Texas Instruments Inc., Villeneuve Loubet
Abstract :
In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-muA range and overall 1200times leakage reduction including process, circuit and system optimization
Keywords :
electrical faults; integrated circuit testing; modems; 65 nm; RTL; clock gating infrastructure; digital base band modem chip; leakage management system; wireless SoC; Circuits; Clocks; Control systems; Energy management; Leakage current; Modems; Power system management; Random access memory; Switches; Voltage;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705386
