Title :
A 15b-Linear, 20MS/s, 1.5b/Stage Pipelined ADC Digitally Calibrated with Signal-Dependent Dithering
Author :
Shu, Yun-Shiang ; Song, Bang-Sup
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, CA
Abstract :
A signal-dependent dithering concept is developed to measure the multiplying DAC (MDAC) gain error of a 1.5b/stage pipelined ADC in background. A 15b, 20MS/s prototype ADC exhibits SFDR and THD of 98 and -92dB with 14.5MHz input. The chip fabricated in 0.18mum CMOS occupies 2.3 times 1.7mm2, and consumes 285mW at 1.8V
Keywords :
analogue-digital conversion; calibration; digital-analogue conversion; 0.18 micron; 1.8 V; 14.5 MHz; 285 mW; DAC calibration; background calibration; digitally calibration; gain error; multiplying DAC; pipelined ADC; signal dependent dithering; Calibration; Capacitors; Computer errors; Electric variables measurement; Gain measurement; Prototypes; Pulse measurements; Pulse modulation; Semiconductor device measurement; Threshold voltage;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705388
