Title :
A 12b, 75MS/s Pipelined ADC Using Incomplete Settling
Author :
Iroaga, Echere ; Murman, Boris
Author_Institution :
Stanford Univ., CA
Abstract :
This paper proposes a mixed-signal technique that exploits incomplete settling to achieve ultra low power residue amplification. In the first stage of the presented 12-bit, 75-MS/s prototype ADC, the employed open-loop gain stage dissipates only 2.9mW from a 3V supply, achieving a 94% power reduction over a typical op-amp implementation. The complete pipelined ADC achieves a measured SNR of 66dB (fin = 1MHz), consumes 273mW and occupies 7.9mm in 0.35mum CMOS
Keywords :
analogue-digital conversion; low-power electronics; mixed analogue-digital integrated circuits; 0.35 micron; 12 bit; 2.9 mW; 273 mW; 3 V; 7.9 mm; incomplete settling; mixed signal technique; op-amp implementation; open loop gain stage; pipelined ADC; ultra low power residue amplification; Calibration; Capacitors; Circuits; Error correction; Gain; High power amplifiers; Operational amplifiers; Power dissipation; Switches; Voltage;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705390
