Gate oxide breakdown behaviour in a mesa SOI CMOS process

Summary form only given. A CMOS process using mesa isolation on lamp-zone-melting recrystallized (ZMR) SOI substrates is discussed. The results of investigations on the gate oxide breakdown behaviour and a technique to improve it when island isolation is used are presented. The technique was used in a 2-μm CMOS process. The gate oxide thickness is 250 A. 16×16 multipliers utilizing 8500 transistors was fabricated on a 4 mm₂ surface. Compared to bulk circuits, they show a 30% improvement in the factor of merit, which is related to the multiplication time and the channel length of the minimal transistors of the circuits