A high-speed processor for digital sine/cosine generation and angle rotation

We present an architecture for high performance sine/cosine generation and angle rotation. Unlike CORDIC-type methods, which implement rotation using a sequence of subrotation stages, each realized, with a butterfly structure, the proposed approach implements the rotation with just two stages. We perform approximately the same number of arithmetic operations in our architecture as in CORDIC-type processors, but our architecture consolidates the operations into small array-multipliers, which can yield a smaller and faster circuit using well-known efficient multiplier implementation techniques (such as Booth encoding).