Title :
Recognition of logic diagrams by identifying loops and rectilinear polylines
Author :
Kim, S.H. ; Suh, J.W. ; Kim, J.H.
Author_Institution :
Dept. of Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejon, South Korea
Abstract :
Proposed is a system that recognizes logic symbols and their interconnections on logic diagrams. The input diagram, digitized by scanner, is converted into a set of line segments through a sequence of picture processing operations. Then symbols and connections are extracted by identifying loops and rectilinear polylines utilizing a model-base in which symbols are graphically described. Experiment with a number of logic diagrams shows that the system correctly recognizes more than 96% of logic symbols and connections on an A4-size diagram with an average complexity within 15 s on a workstation
Keywords :
circuit diagrams; feature extraction; image recognition; logic circuits; A4-size diagram; average complexity; input diagram; line segments; logic diagrams; logic symbols; model-base; picture processing operations; rectilinear polylines; scanner; symbol recognition; Artificial intelligence; Automatic logic units; Computer science; Data mining; Degradation; Graphics; Image converters; Image processing; Image storage; Shape;
Conference_Titel :
Document Analysis and Recognition, 1993., Proceedings of the Second International Conference on
Conference_Location :
Tsukuba Science City
Print_ISBN :
0-8186-4960-7
DOI :
10.1109/ICDAR.1993.395717
