Title :
A 0.5 μm CMOS CNN analog random access memory chip for massive image processing
Author :
Carmona, R. ; Espejo, S. ; Dominguez-Castro, R. ; Rodriguez-Vazque, A. ; Roska, T. ; Kozek, T. ; Chua, L.O.
Author_Institution :
Electron. Res. Lab., California Univ., Berkeley, CA, USA
Abstract :
An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips are available for the CNN Chipset architecture. Time-multiplexed analog routines in the CNN processor require fast and efficient short-time signal storage in an analog buffer. This can be achieved by an extended sample and hold scheme able to address every sample to specific memory locations. Several arrays of capacitors are multiplexed sharing controlling circuitry and I/O buses. The design has the following key parameters: 637 analog memory cells/mm2 with 0.4% accuracy, 100 ns access time and 170 ms storage time (within 1% error)
Keywords :
CMOS analogue integrated circuits; analogue storage; cache storage; cellular neural nets; image processing equipment; neural chips; random-access storage; sample and hold circuits; 0.5 micron; 100 ns; 170 ms; CMOS; CNN universal machine; I/O buses; access time; analog random access memory chip; cache memory; controlling circuitry; massive image processing; sample and hold scheme; short-time signal storage; storage time; time-multiplexed analog routines; Analog memory; Buffer storage; Cache memory; Capacitors; Cellular neural networks; Circuits; Random access memory; Read-write memory; Signal processing; Turing machines;
Conference_Titel :
Cellular Neural Networks and Their Applications Proceedings, 1998 Fifth IEEE International Workshop on
Conference_Location :
London
Print_ISBN :
0-7803-4867-2
DOI :
10.1109/CNNA.1998.685386